PS/2 Controller
Description
This module services as the host side (FPGA board) PS/2 controller, it handles the data transaction to/from the device (a keyboard, mouse or other) according to the PS/2 protocol.
Transmissions are done one byte at a time in 11-bit frames sent serially over the "data" line.
PS/2 frame:
| Bit # | Function |
|---|---|
| 1 | Start bit (always 0) |
| 2 | Data bit 0 (least significant) |
| 3 | Data bit 1 |
| 4 | Data bit 2 |
| 5 | Data bit 3 |
| 6 | Data bit 4 |
| 7 | Data bit 5 |
| 8 | Data bit 6 |
| 9 | Data bit 7 (most significant) |
| 10 | Parity bit (odd parity) |
| 11 | Stop bit (always 1) |
Odd parity means that counting the 1's in the data bits (0 through 7) and the parity bit must amount to an odd number, another way of looking at it is: if the data bits (0 through 7) have an even number of 1's, then the parity bit must be 1.
Having only two wires, one data line and one clock line, control of the data flow from host to device or from the device to the host must be done through them, there are no dedicated control lines for handshaking.
The host has ultimate control over the lines, both data and clock, being able to stop an ongoing transmission from the device to the host, although it's not recommendable.
In this module I've coded, that interruption is not possible if the host is receiving a frame, but the host can take control over the lines immediately after that frame is received.
The line drivers on the device side are open-collector so idle state for clock and data lines is logic high, when the host is not controlling the transmission the PS2Clock and PS2Data ports are high impedance "Z".
Device to host communication:
In this mode, the device always controls both lines.
The device changes the data when the clock is high and the host reads it when clock is low, data should already be stable on the clock falling edges.
In the receiving data mode, the host senses the clock line for the falling edges, when a falling edge is detected it reads a bit from the data line, one after another until reaching the eleventh which is the "Stop bit". That's pretty straightforward.
Host to device communication:
Not so simple is the procedure for sending a command to the device.
First the host drives the clock line low for about 100µs, that inhibits communication from the device.
Next the host drives the data line low, that's a request to send data, when clock and data are low at the same time the device "understands" that the host is trying to send data.
The device waits for the host to release the clock line, this wait takes about 20µs, after that period the device starts clocking (in the figure, the clock line turns red to blue).
The device reads each bit when the clock is high and the host sets the next bit on the falling edges, up until the stop bit, then the host releases the data line.
After the device reads the stop bit, it drives the data line low to acknowledge it received the frame successfully.
Finally the host reads the acknowledge bit.
It might look a bit confusing but after a while it gets into you, if you're interested in more details go to http://www.Computer-Engineering.org/ps2protocol/.
With this module you can connect any PS/2 device to your FPGA board, a keyboard or mouse, a bar-code scanner, etc.
The interface is simple to use and provides you with some control, there is error warning, and besides receiving data you may also send commands.