Program

Reconfigurable systems based on Field-Programmable Gate Arrays (FPGA) operate at a lower clock frequency than non-configurable application-specific integrated circuits; therefore, broad parallelism is evidently required to compete with potential alternatives. Several techniques will be presented that enable parallel circuits and systems to be designed and implemented in FPGAs. In particular, network-based solutions will be discussed on the example of sorting networks. Area/performance tradeoffs of different design approaches will be analyzed.
The respective design process for Xilinx 7-series devices will be explained on the example of Vivado design suite. Different design aspects will be discussed such as specification in VHDL, using IP generator, reading test data from files, development of test benches and simulation, design constraints, synthesis and implementation, analysis of the reports, and hardware programming. Besides of the traditional design entry methods, a possibility of generating hardware modules from software specifications through high-level synthesis (HLS) will be illustrated. A typical HLS design flow will be presented alongside with high-level synthesis coding styles, creating test benches, code debugging, simulation at both high and register-transfer levels, algorithmic and interface synthesis, and design optimization with controlled execution of loops and memory configurations. The example of data sort will be used to show how the results of HLS can be integrated in Vivado projects.

Lectures

Lecture 1

[Slides]

• Introduction to Vivado Design Suite
• Brief overview of Nexys-4 prototyping board
• Specification of embedded and distributed memories in VHDL and with IP Generator
• Initialization of memories from files
• Development of test benches in VHDL and simulation in Vivado

Lecture 2

[Slides]

• Parallel data sort with sorting networks
• Specification in VHDL of parallel data sorters
• Introduction to high-level synthesis
• High-level synthesis coding styles
• Controlling loop execution with synthesis directives
• High-level verification and RTL co-simulation

Labs

Lab 1

[Tasks] [Nexys-4 reference manual] [Nexys-4 master constraints file] [VHDL files required for projects]

• Familiarization with Vivado software
• Modeling in VHDL, synthesis and implementation of finite state machines
• Development of test benches and simulation
• Preparation of test data for experiments
• Synthesis, implementation and test on Nexys-4 prototyping board

Lab 2

[Tasks]

• Preparation of test data for experiments
• Design of parallel data sorters
• Introduction to high-level synthesis
• High-level synthesis and optimization of a data sorter
• Test in FPGA and experiments

References

• V. Sklyarov, I. Skliarova, J. Silva, A. Rjabov, A. Sudnitson, C. Cardoso, "Hardware/Software Co-design for Programmable Systems-on-Chip", TUT Press, 2014.
• Xilinx, Inc., Vivado Design Suite User Guide, Synthesis, UG 901, 2014.
• Xilinx, Inc., Vivado Design Suite Tutorial: Logic Simulation, UG 937, 2014.
• Xilinx, Inc., Vivado Design Suite User Guide. High-Level Synthesis, UG 902, 2014.
• Xilinx, Inc., Introduction to FPGA Design with Vivado High-Level Synthesis, UG 998, 2013.