/*********************************************
*
*             SYSTEM HEADER FILE
*
*       Definitions for the DETUA 188 board
*
*
*     Author: Luis Almeida
*     Date of creation: 97/12/31
*     Modification history:
*
********************************************/





/**** specific 188 control registers  *****/

/* relocation register content - defines control block address */
#define relocat_value   0x20ff
		  /* Control block at 0xff00, No ESC trap, Master interrupt
			controller mode, Control block into I/O space */
/* control registers addresses */
#define relocat_reg     0xfffe   /* relocation register */
#define umcs_reg        0xffa0   /* upper memory chip select register */
#define lmcs_reg        0xffa2   /* lower memory chip select register */
#define pacs_reg        0xffa4   /* peripheral address chip select register */
#define mpcs_reg        0xffa8   /* mode peripheral chip select register */

/* control registers programming values */
#define umcs_value      0xf03d
		  /* 64 Kbytes, 1 wait cycle / ext. ready ign. (F0000-FFFFF) */
#define lmcs_value      0x07fd
		  /* 32 Kbytes, 1 wait cycle / ext. ready ign. (00000-07FFF) */
#define pacs_value      0x023e
		  /*  Peripheral base add = 2000h, 2 wait cycles /ext ready ignored */
#define mpcs_value      0x90be
		  /* Peripherals mapped into I/O space, PCS5 and PCS6 used
		  2 wait cycles / ext. ready ignored */


/****  timer registers *******/
/***  (addresses are absolute when the 188 control block is at 0xff00) ***/
#define tmr0_cntl_reg   0xff56   /* control register add */
#define tmr0_maxcb_reg  0xff54   /* max count register add */
#define tmr0_maxca_reg  0xff52   /* max count register add */
#define tmr0_count_reg  0xff50   /* count register add */
#define tmr0_int_numb  8	/* timer 1 interrupt number */

#define tmr1_cntl_reg   0xff5e   /* control register add */
#define tmr1_maxcb_reg  0xff5c   /* max count register add */
#define tmr1_maxca_reg  0xff5a   /* max count register add */
#define tmr1_count_reg  0xff58   /* count register add */
#define tmr1_int_numb  18	/* timer 1 interrupt number */

#define tmr2_cntl_reg   0xff66   /* control register add */
#define tmr2_maxc_reg  0xff62   /* max count register add */
#define tmr2_count_reg  0xff60   /* count register add */
#define tmr2_int_numb  19	/* timer 2 interrupt number */
#define tmr2_cntl_value 0xe001   /* timer 2 enabled, generate int, run cont */
#define tmr2_maxc_value  1250    /* clock counts per ms */
				/* remember that CPU internal clock = 5MHz */

/****  PIC registers *******/
/***  (addresses are absolute when the 188 control block is at 0xff00) ***/
#define int1_cntl_reg   0xff3a
#define int0_cntl_reg   0xff38
#define tmr_cntl_reg    0xff32
#define in_service_reg  0xff2c
#define mask_reg        0xff28
#define eoi_reg         0xff22

/*#define int1_cntl_value 2*/  /* unmasked, priority=2 */
/*#define int0_cntl_value 1*/  /* unmasked, priority=1 */
#define tmr_cntl_value  0  /* unmasked, highest priority=0 */
#define mask_value      0x00fd  /* all ints masked */
#define in_serv_timers  1  /* 0x0001 - in service timers handling bit */

#define non_spec_eoi 0x8000  /* non-specific eoi */
#define timers_eoi 0x8
#define dma0_eoi 0xa
#define dma1_eoi 0xb
#define int0_eoi 0xc
#define int1_eoi 0xd
#define int2_eoi 0xe
#define int3_eoi 0xf


/****  I/O ports addresses *******/
/***  (according to value programmed into PACS reg) ***/
#define pcs0  0x2000    /* peripheral chip select 0 */
#define pcs1  0x2080    /* peripheral chip select 1 */
#define pcs2  0x2100    /* peripheral chip select 2 */
#define pcs3  0x2180    /* peripheral chip select 3 */
#define pcs4  0x2200    /* peripheral chip select 4 */
/* pcs5 and pcs6 are not avaliable on the board expansion connector */
#define pcs5  0x2280    /* peripheral chip select 3 */
#define pcs6  0x2300    /* peripheral chip select 4 */